The present invention relates to a testing device for testing a semiconductor device.
There have been testing devices each for testing a semiconductor device (hereinafter may also be referred to as a “DUT” standing for a device under test) removably coupled thereto, for example, via a socket. For such testing devices, it is imperative to improve testing efficiency by increasing the number of pins which can be tested simultaneously so as to facilitate mass-production of semiconductor devices. Each testing device is required to offer not only enhanced functions and performance but also flexibility to be compatible with diversified testing processes at reasonable cost.
To enable simultaneous testing of multiple pins while holding the price of the testing device low so as to facilitate testing cost reduction, such a testing device is comprised of plural pin electronics substrates for controlling plural pins, respectively, and a common control substrate for controlling all the pin electronics substrates together.
Each pin electronics substrate includes a memory storing pin data for the corresponding pin. The control substrate includes a program counter which outputs a count value to be an address of the above memory in accordance with an instruction code (see, for example, Japanese Unexamined Patent Publication No. 2004-151990). As operation common to all pins, in each pin electronics substrate, the pin data corresponding to the program counter value is read out and controlled.